The present invention relates to a method of manufacturing a semiconductor wafer, and more particularly to a method of manufacturing a semiconductor wafer with improved gettering properties and a reduced concentration of surface defects.
The fabrication of leading edge integrated circuit devices requires the use of silicon wafers with very low concentrations of mobile contaminants and surface defects. The presence of such contaminants and defects can degrade device performance by causing larger leakage currents and lower breakdown voltages.
Different types of mobile contaminants may be introduced into the silicon wafer during various steps in the wafer manufacturing process. For example, elemental contaminants can be introduced into the silicon lattice during processes such as crystal growing and etching. Some of these contaminants, notably metallic contaminants such as Cu, Ni, Au and Fe, have high mobility in the silicon lattice and can migrate long distances in the silicon wafer when exposed to elevated process temperatures.
Other processes can cause particulate contaminants to be deposited on the surface of the wafer. For example, a wafer holder may chip the edge of the wafer, which can cause silicon particles to be deposited on either the frontside or backside of the wafer. These particles may then migrate across the wafer surface, or onto adjacent wafers in a batch process, possibly contaminating device regions of the wafer.
Various techniques are known for minimizing the potential contamination of device regions of the wafer. For elemental contaminants within the silicon lattice, gettering may be used to immobilize the impurity atoms. Gettering involves the capture of impurity atoms in a silicon wafer by extended defects that are located in regions of the wafer away from device regions. Gettering techniques are generally categorized into two types, extrinsic and intrinsic, depending upon how the gettering defects are created.
Extrinsic gettering generally involves subjecting the backside of a wafer to some sort of process that creates damage or stress in the wafer. The damage or stress creates defects in the silicon lattice that can trap mobile impurities. Commonly used processes for damaging the wafer backside include sandblasting, grooving and abrading the wafer backside. While effective to create stress in the wafer backside, these techniques present several problems. For example, each of these processes involves contacting the wafer backside with a potentially contaminating foreign object. Contaminants deposited on the wafer by the stressing process can then contaminate either the frontside of the wafer or other wafers during a later processing stage. Also, the damage created by these processes may lower the mechanical strength of the wafer. Microcracks and dislocations formed as the wafer tries to relieve the stress created in its backside can make the wafer more prone to warpage during thermal cycles. Furthermore, gettering sites created by these techniques are generally not robustxe2x80x94they may be annealed out of the wafer during thermal cycles, releasing previously immobilized impurities back into the wafer. Finally, the use of these techniques requires adding an additional step to the overall wafer manufacture process, increasing the cost of the process.
Another extrinsic gettering technique involves depositing a film of polycrystalline silicon on the back of the wafer via LPCVD. The grain boundaries and lattice defects in the polycrystalline silicon film act as gettering sites. Applying a polycrystalline silicon film to the backside of a wafer creates more robust extrinsic gettering sites than damaging of the backside of the wafer, as the polycrystalline silicon film is less affected by later thermal cycling than backside damage. However, the use of this technique still requires adding an additional LPCVD step to the wafer manufacturing process, increasing the cost of the overall process.
Intrinsic gettering, on the other hand, involves the intentional precipitation of oxygen present in the silicon lattice to create impurity-trapping defects within the bulk silicon. The oxygen is incorporated into the silicon lattice during the crystal growth process by the degradation of the SiO2 crucible used for the crystal growth. Using various thermal cycling techniques, the oxygen can be made to precipitate in regions close to, yet separated from, device regions of the wafer. The oxygen precipitates cause lattice strain, which in turn creates defects that can trap mobile impurities. Typically, the defects are formed by a three-step thermal cycle. First, a high-temperature step is used to remove oxygen from the surface regions of the wafer, where it can harm circuit performance. Next, a lower temperature step is used to nucleate the oxygen precipitates. Finally, another high-temperature step is used to increase the size of the precipitates to create lattice strain.
Intrinsic gettering offers several advantages over extrinsic gettering. For example, intrinsic gettering may be employed without any additional processing steps besides heating steps. Also, the volume of the bulk wafer as a sink for impurities is much larger than the volume of the damaged area when backside extrinsic gettering is used, thus allowing more impurities to be trapped. However, the necessary thermal cycles increase the cost of the wafer manufacturing process. Furthermore, the thermal processes must be carefully controlled so that the oxygen precipitates do not become too large or too dense, as this can lead to later warping of the wafers. Nitrogen doping of the melt from which a silicon crystal is formed can help cause oxygen precipitates to nucleate during crystal pulling without additional thermal processing, but the size of the precipitates may be difficult to control.
It is generally desirable to provide both intrinsic and extrinsic gettering mechanisms to trap as many mobile contaminants in the wafer as possible. However, because of the extra process steps involved with each technique, the provision of both types of gettering mechanisms may make the overall wafer manufacturing process prohibitively expensive.
Surface defects on a wafer may have similar deleterious effects on circuit performance as those caused by mobile impurities. One common type of surface defect is known as crystal originated particles, or COP. COP result from small octahedral voids that form during the crystal growth process due to the agglomeration of point defects within the silicon lattice. When a wafer surface is cleaned using the SC-1 technique, the voids are exposed as COP. The presence and concentrations of COP on a wafer surface can be measured using optical techniques such as laser scattering tomography, in which the defects scatter incident laser light. The presence of these voids within the bulk silicon of a wafer has some advantages, as oxygen tends to precipitate in the walls of the voids, creating gettering sites within the bulk silicon. However, the voids should not be too large in size, as larger voids tend to degrade circuit performance more than smaller voids. Furthermore, the presence of COP on the surface of the silicon is not desirable, as the COP may degrade circuit performance. COP can be removed from the surface of a silicon wafer by depositing an epitaxial film over the top surface of the wafer, but large COP are difficult and expensive to cover with this method. Thus it would be desirable to have a method of economically manufacturing a silicon wafer that offers robust gettering properties and low concentrations of surface defects.
The present invention provides a method of manufacturing a silicon wafer. The method comprises adding polycrystalline silicon to a crucible; adding a nitrogen-containing dopant to the crucible; heating the crucible to form a nitrogen-doped silicon melt; pulling a silicon crystal from the melt according to the Czochralski technique; forming a silicon wafer from the silicon crystal, wherein the silicon wafer includes a front surface and a back surface; placing the silicon wafer into a deposition chamber; heating the wafer; and simultaneously depositing an epitaxial first film of a desired compound onto the front surface of the wafer and a second film of the desired compound onto the back surface of the wafer.